`timescale 1ns / 1ps



module MUX2X32(A0,A1,S,Y);
    input [31:0]A0,A1;
    input S;
    output [31:0]Y;
    assign Y = (S == 0)? A0 : A1;
endmodule




`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2021/05/30 11:43:12
// Design Name: 
// Module Name: test
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module ts;
reg [31:0] A0;
reg [31:0] A1;
reg Select;
wire [31:0] Y;
MUX2X32 unit( .A0(A0),
    .A1(A1),
    .Select(Select),
    .Y(Y));
initial
begin
#10 Select=0;
#10 Select=1;
end
endmodule





`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2021/05/30 11:31:49
// Design Name: 
// Module Name: MUX2X32
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module MUX2X32(
    input [31:0] A0,
    input [31:0] A1,
    input Select,
    output reg [31:0] Y
    );
    always@(*)
    begin
    case(Select)
    1'b0:Y=A0;
    1'b1:Y=A1;
    endcase
    end
endmodule
